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| P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM Rev. 03 -- 17 December 2004 Product data 1. General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost. 2. Features s 1 kB byte-erasable Flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. s 128-byte RAM data memory. s Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output. s 23-bit system timer that can also be used as a Real-Time clock. s Two analog comparators with selectable inputs and reference source. s Enhanced UART with fractional baudrate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC913, P89LPC914). s SPI communication port. s Internal RC oscillator (factory calibrated to 1 %) option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). s Up to 12 I/O pins when using internal oscillator and reset options. 3. Additional features * 14-pin TSSOP packages. * A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz (167 ns to 333 ns at 12 MHz). This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. * In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core * Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. * Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values. * Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. * Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 A (total Power-down with voltage comparators disabled). * Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. * Configurable on-chip oscillator with frequency range options selected by user programmed Flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz (P89LPC912, P89LPC913). * Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. * Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. * Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. * LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. * Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. * Only power and ground connections are required to operate the P89LPC912/913/914 when internal reset option is selected. * Four interrupt priority levels. * Four keypad interrupt inputs. * Second data pointer. * Schmitt trigger port inputs. * Emulation support. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 2 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 4. Ordering information Table 1: Ordering information Package Name P89LPC912FDH P89LPC913FDH P89LPC914FDH TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Type number 4.1 Ordering options Table 2: Type number P89LPC912FDH P89LPC913FDH P89LPC914FDH 0 MHz to 12 MHz Temperature range -40 C to +85 C Frequency 0 MHz to 18 MHz 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 3 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 5. Block diagram P89LPC912 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH INTERNAL BUS 128-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os SPI REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) CRYSTAL OR RESONATOR CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR 002aaa472 Fig 1. P89LPC912 block diagram. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 4 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core P89LPC913 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH INTERNAL BUS 128-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os UART SPI REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) CRYSTAL OR RESONATOR CONFIGURABLE OSCILLATOR ON-CHIP RC OSCILLATOR 002aaa473 Fig 2. P89LPC913 block diagram. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 5 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core P89LPC914 HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH INTERNAL BUS 128-BYTE DATA RAM PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os UART SPI REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR KEYPAD INTERRUPT ANALOG COMPARATORS PROGRAMMABLE OSCILLATOR DIVIDER CPU CLOCK POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) ON-CHIP RC OSCILLATOR 002aaa474 Fig 3. P89LPC914 block diagram. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 6 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 6. Pinning information 6.1 Pinning handbook, halfpage P2.2/MOSI 1 SPICLK/P2.5 2 14 P2.3/MISO 13 P0.2/CIN2A/KBI2 P89LPC912FDH RST/P1.5 3 VSS 4 P0.6/CMP1/KBI6 5 P1.2/T0 6 XTAL1/P3.1 7 12 P0.4/CIN1A/KBI4 11 P0.5/CMPREF/KBI5 10 VDD 9 8 P2.4/SS CLKOUT/XTAL2/P3.0 002aaa478 Fig 4. P89LPC912 TSSOP14 pin configuration. handbook, halfpage P2.2/MOSI 1 SPICLK/P2.5 2 14 P2.3/MISO 13 P0.2/CIN2A/KBI2 P89LPC913FDH RST/P1.5 3 VSS 4 P0.6/CMP1/KBI6 5 P1.1/RXD 6 XTAL1/P3.1 7 12 P0.4/CIN1A/KBI4 11 P0.5/CMPREF/KBI5 10 VDD 9 8 P1.0/TXD CLKOUT/XTAL2/P3.0 002aaa479 Fig 5. P89LPC913 TSSOP14 pin configuration. handbook, halfpage P2.2/MOSI 1 SPICLK/P2.5 2 14 P2.3/MISO 13 P0.2/CIN2A/KBI2 P89LPC914FDH RST/P1.5 3 VSS 4 P0.6/CMP1/KBI6 5 P1.1/RXD 6 P1.2/T0 7 12 P0.4/CIN1A/KBI4 11 P0.5/CMPREF/KBI5 10 VDD 9 8 P1.0/TXD P2.4/SS 002aaa480 Fig 6. P89LPC914 TSSOP14 pin configuration. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 7 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 6.2 Pin description Table 3: Symbol P0.2, P0.4 to P0.6 P89LPC912 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O I I 12 I/O I I 11 I/O I I 5 I/O O I P1.2, P1.5 P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. I/O Port 1: Port 1 is a 2-bit I/O port with P1.2 having a user-configurable output type as (P1.2); noted below. During reset Port 1 latches are configured in the input only mode with I (P1.5) the internal pull-up disabled. The operation of the P1.2 input and outputs depends upon the port configuration selected. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 6 I/O I/O 3 I I P1.2 -- Port 1 bit 2. (Open drain when used as an output.) T0 -- Timer/counter 0 external count input or overflow output. (Open drain when used as outputs.). P1.5 -- Port 1 bit 5. (Input only.) RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 8 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 3: Symbol P89LPC912 pin description...continued Pin Type I/O Description Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 1 I/O I/O 14 I/O I/O 9 2 I/O I I/O I/O P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 8 I/O O O P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. P2.2 to P2.5 P3.0 to P3.1 I/O 7 I/O I VSS VDD 4 10 I I 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 9 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 4: Symbol P89LPC913 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O I I 12 I/O I I 11 I/O I I 5 I/O O I P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. Port 1: Port 1 is a 3-bit I/O port with a user-configurable output type, except for P1.5 noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 9 6 3 I/O O I/O I I I P1.0 -- Port 1 bit 0. TxD -- Transmitter output for the serial port. P1.1 -- Port 1 bit 1. RxD -- Receiver input for the serial port. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. P0.2, P0.4 to P0.6 P1.0, P1.1, P1.5 I/O (P1.0, P1.1); I (P1.5) 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 10 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 4: Symbol P2.2, P2.3, P2.5 P89LPC913 pin description...continued Pin Type I/O Description Port 2: Port 2 is a 3-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 13 I/O I/O 14 I/O I/O 16 I/O I/O P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 8 I/O O O P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. P3.0 to P3.1 I/O 7 I/O I VSS VDD 4 10 I I 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 11 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 5: Symbol P89LPC914 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 13 I/O I I 12 I/O I I 11 I/O I I 5 I/O O I P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. Port 1: Port 1 is a 4-bit I/O port with a user-configurable output type, except for three pins noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 9 6 7 I/O O I/O I I/O I/O 3 I I P1.0 -- Port 1 bit 0. TxD -- Transmitter output for the serial port. P1.1 -- Port 1 bit 1. RxD -- Receiver input for the serial port. P1.2 -- Port 1 bit 2. (Open drain when used as an output.) T0 -- Timer/counter 0 external count input or overflow output. (Open drain when used as outputs.) P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. P0.2, P0.4 to P0.6 P1.0 to P1.2, P1.5 I/O (P1.0 to P1.2); I (P1.5) 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 12 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 5: Symbol P89LPC914 pin description...continued Pin Type I/O Description Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 1 I/O I/O 14 I/O I/O 8 2 I/O I I/O I/O P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. P2.2 to P2.5 VSS VDD 4 10 I I 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 13 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 7. Logic symbols VDD VSS PORT 1 T0 RST P89LPC912 KBI2 KBI4 KBI5 KBI6 CIN2A CIN1A CMPREF CMP1 PORT 0 CLKOUT XTAL2 XTAL1 MOSI MISO SS SPICLK PORT 3 002aaa475 Fig 7. P89LPC912 logic symbol. VDD VSS PORT 1 PORT 2 P89LPC913 KBI2 KBI4 KBI5 KBI6 CIN2A CIN1A CMPREF CMP1 PORT 0 TxD RxD RST PORT 2 CLKOUT XTAL2 XTAL1 PORT 3 MOSI MISO SPICLK 002aaa476 Fig 8. P89LPC913 logic symbol. VDD VSS P89LPC914 KBI2 KBI4 KBI5 KBI6 CIN2A CIN1A CMPREF CMP1 PORT 0 TxD RxD T0 RST PORT 1 MOSI MISO SS SPICLK 002aaa477 Fig 9. P89LPC914 logic symbol. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 PORT 2 14 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 7.1 Product comparison Table 6 highlights the differences between these three devices. For a complete list of device features, please see Section 2 "Features" on page 1. Table 6: Product comparison External X2 CLKOUT crystal pins X X X X T0 PWM output X X SPI with SS pin X X SPI without SS pin X UART TxD X X RxD X X Max fosc (MHz) 18 18 12 Type number P89LPC912 P89LPC913 P89LPC914 8. Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: * User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows: - `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 15 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 14468 Philips Semiconductors Table 7: P89LPC912 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program Flash address high Program Flash address low Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* IP0H IP1* IP1H KBCON Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Keypad control register E5H Bit address A8H Bit address E8H Bit address B8H B7H Bit address F8H F7H 94H AF EA EF BF FF AE EWDRT EE BE PWDRT PWDRTH FE AD EBO ED BD PBO PBOH FD AC EC BC FC AB ET1 EB ESPI BB PT1 PT1H FB PSPI PSPIH AA EA EC BA FA PC PCH A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL A8 E8 B8 F8 KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00 00000000 83H 82H E7H E6H E4H BUSY FMCMD. 7 HVA HVE SV OI FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. 6 4 3 2 1 0 00 00000000 00 00 00 00 70 00000000 00000000 00000000 00000000 01110000 E0H A2H Bit address F0H ACH ADH 95H CE1 CE2 CN1 CN2 OE1 CO1 CO2 CMF1 CMF2 CLKLP F7 F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00[1] 00[1] 00 00000000 xx000000 xx000000 00000000 Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary 8-bit microcontrollers with two-clock 80C51 core P89LPC912/913/914 16 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 7: P89LPC912 Special function registers...continued * indicates SFRs that are bit addressable. Name KBMASK KBPATN P0* Description Keypad interrupt mask register Keypad pattern register Port 0 SFR addr. 86H 93H Bit address 80H Bit address P1* P2* Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data 17 of 63 9397 750 14468 Philips Semiconductors Bit functions and addresses MSB LSB Reset value Hex 00 FF Binary 00000000 11111111 87 86 CMP1/ KB6 85 CMPREF/ KB5 95 RST A5 SPICLK B5 84 CIN1A/ KB4 94 A4 SS B4 83 82 CIN2A/ KB2 81 80 [1] 97 A7 B7 96 A6 B6 (P0M1.6) (P0M2.6) 93 A3 MISO B3 92 T0 A2 MOSI B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) 91 A1 B1 XTAL1 90 [1] Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Stack pointer 90H Bit address A0H Bit address B0H 84H 85H 91H 92H A4H A5H B1H B2H 87H B5H Bit address D0H F6H DFH D1H D2H D3H 81H RTCPD D7 CY RTCF D6 AC RTCS1 A0 [1] B0 XTAL2 [1] P3* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SP (P0M1.5) (P0M1.4) (P0M2.5) (P0M2.4) FF 00 D3[1] 00[1] FF 00 (P3M1.1) (P3M1.0) 03[1] 00 00[1] 00 00 [2] 11111111 00000000 11x1xx11 00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00 00000000 00000000 00000000 xx00000x 8-bit microcontrollers with two-clock 80C51 core (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) P89LPC912/913/914 (P3M2.1) (P3M2.0) 00[1] BOPD VCPD D5 F0 PT0AD.5 BOF RTCS0 BOI D4 RS1 PT0AD.4 POF GF1 D3 RS0 GF0 SPPD D2 OV PT0AD.2 R_WD PMOD1 D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN 60[1][5] 011xxx00 00[5] 00[5] 07 00000000 00000000 00000111 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 7: P89LPC912 Special function registers...continued * indicates SFRs that are bit addressable. Name SPCTL SPSTAT SPDAT TAMOD TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2 [1] [2] [3] (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 18 of 63 9397 750 14468 Philips Semiconductors Description SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2 SFR addr. E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H Bit functions and addresses MSB SSIG SPIF 8F TF1 SPEN WCOL 8E TR1 DORD 8D TF0 MSTR 8C TR0 CPOL 8B CPHA 8A SPR1 89 LSB SPR0 T0M2 88 - Reset value Hex 04 00 00 00 00 00 00 00 00 Binary 00000100 00xxxxxx 00000000 xxx0xxx0 00000000 00000000 00000000 00000000 00000000 00000000 Bit address PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 - T0GATE TRIM.3 - T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00 [4] [5] [3] [5] FF 11111111 8-bit microcontrollers with two-clock 80C51 core [4] [5] All ports are in input only (high impedance) state after power-up. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset. P89LPC912/913/914 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 14468 Philips Semiconductors Table 8: P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program Flash address high Program Flash address low Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high E5H Bit address A8H Bit address E8H Bit address B8H B7H AF EA EF BF AE EWDRT EE EST BE PWDRT PWDRTH AD EBO ED BD PBO PBOH AC ES/ESR EC BC PS/PSR PSH/ PSRH AB ET1 EB ESPI BB PT1 PT1H AA EA EC BA A9 ET0 E9 EKBI B9 PT0 PT0H A8 E8 B8 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00 00000000 83H 82H E7H E6H E4H BUSY FMCMD. 7 HVA HVE SV OI FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. 6 4 3 2 1 0 00 00000000 00 00 00 00 70 00000000 00000000 E0H A2H Bit address F0H BEH BFH BDH ACH ADH 95H CE1 CE2 CN1 CN2 OE1 SBRGS CO1 BRGEN CMF1 CMF2 CLKLP F7 EBRR F6 F5 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[6] 00[1] 00[1] 00 00000000 00000000 00000000 xxxxxx00 xx000000 xx000000 00000000 Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary 8-bit microcontrollers with two-clock 80C51 core 00000000 00000000 01110000 P89LPC912/913/914 19 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8: P89LPC913 Special function registers...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IP1* IP1H KBCON KBMASK KBPATN P0* Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data 20 of 63 9397 750 14468 Philips Semiconductors Bit functions and addresses MSB FF FE PST PSTH FD FC FB PSPI PSPIH FA PC PCH F9 PKBI PKBIH PATN _SEL LSB F8 KBIF Reset value Hex 00[1] 00[1] 00[1] 00 FF Binary 00x00000 00x00000 xxxxxx00 00000000 11111111 Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 F8H F7H 94H 86H 93H Bit address 80H Bit address 87 86 CMP1/ KB6 85 CMPREF/ KB5 95 RST A5 SPICLK B5 84 CIN1A/ KB4 94 A4 B4 83 82 CIN2A/ KB2 81 80 [1] 97 A7 B7 96 A6 B6 (P0M1.6) (P0M2.6) 93 A3 MISO B3 92 A2 MOSI B2 (P0M1.2) (P0M2.2) 91 RxD A1 B1 XTAL1 90 TxD A0 [1] [1] P1* P2* P3* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A 90H Bit address A0H Bit address B0H 84H 85H 91H 92H A4H A5H B1H B2H 87H B5H SMOD1 RTCPD SMOD0 - B0 XTAL2 [1] 8-bit microcontrollers with two-clock 80C51 core (P0M1.5) (P0M1.4) (P0M2.5) (P0M2.4) FF 00 (P1M1.1) (P1M1.0) D3[1] FF 00 (P3M1.1) (P3M1.0) 03[1] 00 00[1] (P3M2.1) (P3M2.0) 00[1] (P1M2.1) (P1M2.0) 00[1] 11111111 00000000 11x1xx11 00x0xx00 11111111 00000000 xxxxxx11 xxxxxx00 00000000 00000000 P89LPC912/913/914 (P2M1.5) (P2M2.5) (P2M1.3) (P2M1.2) (P2M2.3) (P2M2.2) BOPD VCPD BOI - GF1 - GF0 SPPD PMOD1 SPD PMOD0 - xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8: P89LPC913 Special function registers...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP SPCTL SPSTAT SPDAT TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 21 of 63 9397 750 14468 Philips Semiconductors Bit functions and addresses MSB D7 CY RTCF D6 AC RTCS1 D5 F0 PT0AD.5 BOF RTCS0 D4 RS1 PT0AD.4 POF D3 RS0 R_BK D2 OV PT0AD.2 R_WD D1 F1 R_SF ERTC LSB D0 P R_EX RTCEN Reset value Hex 00 00 [3] Binary 00000000 xx00000x Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register D0H F6H DFH D1H D2H D3H A9H B9H 99H 60[1][6] 011xxx00 00[6] 00[6] 00 00 xx 00000000 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000100 00xxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bit address 98H BAH 81H E2H E1H E3H Bit address 88H 8CH 8DH 8AH 8BH 89H 96H A7H 9F SM0/FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 8-bit microcontrollers with two-clock 80C51 core SSIG SPIF 8F TF1 SPEN WCOL 8E TR1 DORD 8D TF0 MSTR 8C TR0 CPOL 8B - CPHA 8A - SPR1 89 - SPR0 88 - 04 00 00 00 00 00 00 00 P89LPC912/913/914 PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 - T0GATE TRIM.3 - T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00 [5] [6] [4] [6] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8: P89LPC913 Special function registers...continued * indicates SFRs that are bit addressable. Name WDL WFEED1 WFEED2 [1] [2] [3] [4] [5] [6] Product data Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 14468 Philips Semiconductors Description Watchdog load Watchdog feed 1 Watchdog feed 2 SFR addr. C1H C2H C3H Bit functions and addresses MSB LSB Reset value Hex FF Binary 11111111 All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset. 8-bit microcontrollers with two-clock 80C51 core P89LPC912/913/914 22 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data Rev. 03 -- 17 December 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 14468 Philips Semiconductors Table 9: P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* BRGR0[2] BRGR1[2] CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program Flash address high Program Flash address low Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high E5H Bit address A8H Bit address E8H Bit address B8H B7H AF EA EF BF AE EWDRT EE EST BE PWDRT PWDRTH AD EBO ED BD PBO PBOH AC ES/ESR EC BC PS/PSR PSH/ PSRH AB ET1 EB ESPI BB PT1 PT1H AA EA EC BA A9 ET0 E9 EKBI B9 PT0 PT0H A8 E8 B8 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 00 00000000 83H 82H E7H E6H E4H BUSY HVA HVE SV FMCMD.1 OI FMCMD. 0 00 00000000 FMCMD. FMCMD. FMCMD.5 FMCMD. FMCMD. FMCMD. 7 6 4 3 2 00 00 00 00 70 00000000 00000000 E0H A2H Bit address F0H BEH BFH BDH ACH ADH 95H CE1 CE2 CN1 CN2 OE1 SBRGS CO1 CO2 BRGEN CMF1 CMF2 F7 EBRR F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[6] 00[1] 00[1] 00 00000000 00000000 00000000 xxxxxx00 xx000000 xx000000 00000000 Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary BRGCON Baud rate generator control 8-bit microcontrollers with two-clock 80C51 core 00000000 00000000 01110000 P89LPC912/913/914 23 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 9: P89LPC914 Special function registers...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IP1* IP1H KBCON KBMASK KBPATN P0* Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 F8H F7H 94H 86H 93H Bit address 80H Bit address P1* P2* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 24 of 63 9397 750 14468 Philips Semiconductors Bit functions and addresses MSB FF FE PST PSTH FD FC FB PSPI PSPIH FA PC PCH F9 PKBI PKBIH PATN_SEL LSB F8 KBIF Reset value Hex 00[1] 00[1] 00[1] 00 FF Binary 00x00000 00x00000 xxxxxx00 00000000 11111111 87 86 CMP1/ KB6 85 CMPREF/ KB5 95 RST A5 SPICLK 84 CIN1A/ KB4 94 A4 SS 83 82 CIN2A/ KB2 81 80 [1] 97 A7 96 A6 (P0M1.6) (P0M2.6) 93 A3 MISO 92 T0 A2 MOSI (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) 91 RxD A1 90 TxD A0 [1] [1] Port 1 Port 2 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register 90H Bit address A0H 84H 85H 91H 92H A4H A5H 87H B5H Bit address D0H F6H DFH D1H D2H D3H A9H SMOD1 RTCPD D7 CY RTCF SMOD0 D6 AC RTCS1 (P0M1.5) (P0M1.4) (P0M2.5) (P0M2.4) FF 00 (P1M1.1) (P1M2.1) (P1M1.0) D3[1] (P1M2.0) 00[1] FF 00 PMOD1 SPD D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN 00 00 [3] 11111111 00000000 11x1xx11 00x0xx00 11111111 00000000 00000000 00000000 00000000 xx00000x 8-bit microcontrollers with two-clock 80C51 core (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) BOPD VCPD D5 F0 PT0AD.5 BOF RTCS0 BOI D4 RS1 PT0AD.4 POF GF1 D3 RS0 R_BK GF0 SPPD D2 OV PT0AD.2 R_WD - P89LPC912/913/914 00 00[1] 60[1][6] 011xxx00 00[6] 00[6] 00 00000000 00000000 00000000 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 9: P89LPC914 Special function registers...continued * indicates SFRs that are bit addressable. Name SADEN SBUF SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2 [1] [2] [3] [4] [5] [6] (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 25 of 63 9397 750 14468 Philips Semiconductors Description Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2 SFR addr. B9H 99H Bit functions and addresses MSB LSB Reset value Hex 00 xx Binary 00000000 xxxxxxxx 00000000 00000000 00000111 00000100 00xxxxxx 00000000 xxx0xxx0 00000000 00000000 00000000 00000000 00000000 00000000 Bit address 98H BAH 81H E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H 9F SM0/FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 SSIG SPIF 8F TF1 SPEN WCOL 8E TR1 DORD 8D TF0 MSTR 8C TR0 CPOL 8B - CPHA 8A - SPR1 89 - SPR0 T0M2 88 - 04 00 00 00 00 00 00 00 00 Bit address 8-bit microcontrollers with two-clock 80C51 core PRE2 PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 - T0GATE TRIM.3 - T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF T0M0 TRIM.0 WDCLK 00 [5] [6] [4] [6] P89LPC912/913/914 FF 11111111 All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset. Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9. Functional description Remark: Please refer to the P89LPC912/913/914 User's Manual for a more detailed functional description. 9.1 Enhanced CPU The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 9.2 Clocks 9.2.1 Clock definitions The P89LPC912/913/914 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 10, 11, and 12) and can also be optionally divided to a slower frequency (see Section 9.7 "CPU Clock (CCLK) modification: DIVM register"). Note: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. PCLK -- Clock for the various peripheral devices and is CCLK/2 9.2.2 CPU clock (OSCCLK) The P89LPC912/913/914 provide user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip Watchdog oscillator and an on-chip RC oscillator. In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an external crystal or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz. 9.2.3 Low speed oscillator option (P89LPC912, P89LPC913) This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration. 9.2.4 Medium speed oscillator option (P89LPC912, P89LPC913) This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration. 9.2.5 High speed oscillator option (P89LPC912, P89LPC913) This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 26 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. 9.2.6 Clock output (P89LPC912, P89LPC913) The P89LPC912 supports a user selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC912. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. 9.3 On-chip RC oscillator option The P89LPC912/913/914 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, 2.5 %. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. 9.4 Watchdog oscillator option The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed. 9.5 External clock input option (P89LPC912, P89LPC913) In this configuration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 27 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core XTAL1 XTAL2 High freq. Med. freq. Low freq. RTC Oscillator clock OSCCLK DIVM CPU clock CCLK CPU /2 WDT PCLK Peripheral clock RC OSCILLATOR (7.3728 MHz) WATCHDOG OSCILLATOR (400 kHz) SPI TIMER 0 and TIMER 1 002aaa481 Fig 10. Block diagram of oscillator control (P89LPC912). XTAL1 XTAL2 High freq. Med. freq. Low freq. RTC Oscillator clock OSCCLK DIVM CPU clock CCLK CPU RC OSCILLATOR (7.3728 MHz) WATCHDOG OSCILLATOR (400 kHz) CCLK 2 WDT PCLK Peripheral clock UART BAUD RATE GENERATOR SPI TIMER 0 and TIMER 1 002aaa482 Fig 11. Block diagram of oscillator control (P89LPC913). 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 28 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core RTC Oscillator clock RC OSCILLATOR (7.3728 MHz) OSCCLK DIVM CPU clock CCLK CPU 2 WDT PCLK CCLK Peripheral clock WATCHDOG OSCILLATOR (400 kHz) UART BAUD RATE GENERATOR SPI TIMER 0 and TIMER 1 002aaa483 Fig 12. Block diagram of oscillator control (P89LPC914). 9.6 CPU Clock (CCLK) wake-up delay The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it stabilizes, depending to the clock source used. If the clock source is any of the three crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 60 to 100 s. If the clock source is either the internal RC oscillator, Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100 s. 9.7 CPU Clock (CCLK) modification: DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution. 9.8 Low power select The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the power consumption further. On any reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. 9.9 Memory organization The various P89LPC912/913/914 memory spaces are as follows: * DATA 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 29 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core * SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. * CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory. 9.10 Interrupts The P89LPC912/913/914 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 9.10.1 External interrupt inputs The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 9.13 "Power reduction modes" for details. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 30 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBF EKB EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 SPIF ESPI WAKE-UP (IF IN POWER-DOWN) INTERRUPT TO CPU 002aaa484 Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC912). BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBF EKB EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI & RI/RI ES/ESR TI EST SPIF ESPI INTERRUPT TO CPU WAKE-UP (IF IN POWER-DOWN) 002aaa485 Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC913, P89LPC914). 9.11 I/O ports The P89LPC912 and P89LPC913 devices have 4 I/O ports: Port 0, Port 1, Port 2 and Port 3. The exact number of I/O pins available depends on the clock and reset options chosen, as shown in Table 10. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 31 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Number of I/O pins available (P89LPC912, P89LPC913) Reset option Number of I/O pins (14-pin package) 12 11 11 10 10 9 Table 10: Clock source On-chip oscillator or watchdog oscillator External clock input No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported[1] Low/medium/high speed oscillator (external crystal or resonator) [1] Required for operation above 12 MHz. The P89LPC914 has 3 I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends on the reset option chosen, as shown in Table 11. Table 11: Number of I/O pins available (P89LPC914) Number of I/O pins (14-pin package) 12 11 supported[1] Reset option No external reset (except during power-up) External RST pin [1] Required for external clock frequency above 12 MHz. 9.11.1 Port configurations Except as listed below, every I/O pin on the P89LPC912/913/914 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5/RST can only be an input and cannot be configured. P1.2/T0 may only be configured to be either input-only or open drain (P89LPC912, P89LPC914). 9.11.2 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC912/913/914 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 32 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit. 9.11.3 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic `0'. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit. 9.11.4 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit. 9.11.5 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic `1'. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit. 9.11.6 Port 0 analog functions The P89LPC912/913/914 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described in Section 9.11.4 "Input-only configuration". Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to `0's to enable digital functions. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 33 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.11.7 Additional port features After power-up, all pins are in Input-Only mode. After power-up all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. * P1.2/T0 is configurable for either input-only or open-drain (P89LPC912, P89LPC914). Every output on the P89LPC912/913/914 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 13 "DC electrical characteristics" for detailed specifications. All port pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times. 9.12 Power monitoring functions The P89LPC912/913/914 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect. 9.12.1 Brownout detection The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however, it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the brownout condition occurs when VDD falls below the brownout trip voltage, VBO (see Table 13 "DC electrical characteristics"), and is negated when VDD rises above VBO. If the P89LPC912/913/914 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 13 "DC electrical characteristics" for specifications. 9.12.2 Power-on detection The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. 9.13 Power reduction modes The P89LPC912/913/914 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 34 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.13.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. 9.13.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC912/913/914 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down. These include: Brownout detect, Watchdog Timer, Comparators (note that Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. 9.13.3 Total Power-down mode This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power-down. 9.14 Reset The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 35 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Reset can be triggered from the following sources: * External reset pin (during power-up or if user configured via UCFG1. This option must be used for an oscillator frequency above 12 MHz.) * * * * * Power-on detect Brownout detect Watchdog Timer Software reset UART break character detect reset (P80LPC913, P89LPC914). For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a `0' to the corresponding bit. More than one flag bit may be set: * During a power-on reset, both POF and BOF are set but the other flag bits are cleared. * For any other reset, previously set flag bits that have not been cleared will remain set. 9.15 Timers/counters 0 and 1 The P89LPC912/913/914 devices have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to automatically toggle the T0 pin upon timer overflow has been added (P89LPC912, P89LPC914). In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register of Timer 0 is incremented in response to a 1-to-0 transition at its external input pin, T0. This external input is sampled once very machine cycle. Timer 0 has four operating modes (modes 0, 1, 2, and 3) on the P89LPC913). Timer 0 has five operating modes (modes 0, 1, 2, 3, and 6 on the P89LPC912 and P89LPC914. Timer 1 has four operating modes (modes 0, 1, 2, and 3) on all devices. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. 9.15.1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1. 9.15.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 9.15.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 36 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.15.4 Mode 3 When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator. 9.15.5 Mode 6 (P89LPC912, P89LPC914) In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks. 9.15.6 Timer overflow toggle output (P89LPC912, P89LPC914) Timers 0 can be configured to automatically toggle the T0 output whenever a timer overflow occurs. The same device pins that are used for the T0 count input is also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 9.16 Real-Time clock/system timer The P89LPC912/913/914 devices have a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all `0's, the counter will be reloaded again and the RTCF flag will be set. On the P89LPC914 the clock source for this counter is the CPU clock (CCLK). On the P89LPC912 and P89LPC913 devices, the clock source for this counter can either be the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state. 9.17 UART (P89LPC913, P89LPC914) The P89LPC913 and P89LPC914 devices have an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC913 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CCLK/32 or CCLK/16. 9.17.1 Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 37 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.17.2 Mode 1 10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical `0'), 8 data bits (LSB first), and a stop bit (logical `1'). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 9.17.5 "Baud rate generator and selection"). 9.17.3 Mode 2 11 bits are transmitted (through TxD) or received (through RxD): start bit (logical `0'), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical `1'). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of `0' or `1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CCLK frequency, as determined by the SMOD1 bit in PCON. 9.17.4 Mode 3 11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical `0'), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical `1'). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in section Section 9.17.5 "Baud rate generator and selection"). 9.17.5 Baud rate generator and selection The P89LPC913 and P89LPC914 devices have an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK. Timer 1 Overflow (PCLK-based) Baud Rate Generator (CCLK-based) SMOD1 = 1 SBRGS = 0 Baud Rate Modes 1 and 3 2 SMOD1 = 0 SBRGS = 1 002aaa419 Fig 15. Baud rate sources for UART (Modes 1, 3). 9.17.6 Framing error Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is `1', framing errors can be made available in SCON.7, respectively. If SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is `0'. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 38 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.17.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device. 9.17.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = `0'), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = `0'). 9.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data. 9.17.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. 9.18 Serial Peripheral Interface (SPI) P89LPC912/913/914 provides another high-speed serial communication interface--the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master or 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 39 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core S M PIN CONTROL LOGIC CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPEN SPI clock (master) SELECT SPR1 SPR0 clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus SPR0 SSIG SPI CONTROL WCOL SPIF MSTR SPEN SPI STATUS REGISTER SPI interrupt request 002aaa497 Fig 16. SPI block diagram (P89LPC912, P89LPC914). S M PIN CONTROL LOGIC CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SPI clock (master) SELECT SPR1 SPR0 clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus SPR0 SSIG SPI CONTROL WCOL SPIF MSTR SPEN SPI STATUS REGISTER SPI interrupt request SPEN 002aaa498 Fig 17. SPI block diagram (P89LPC913). The SPI interface has four pins: SPICLK, MOSI, MISO, and SS: * SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 40 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions. * SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 18, 19, and 20. * The 89LPC913 does not have the slave select pin, SS. The SPI interface is set to Master mode and an I/O pin may be used to implement the SS function. Typical connections are shown in Figure 18 and 19. 9.18.1 Typical SPI configurations Master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI Slave 8-BIT SHIFT REGISTER SPICLK SPI CLOCK GENERATOR PORT SPICLK SS 002aaa435 Fig 18. SPI single master single slave configuration. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 41 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI Slave 8-BIT SHIFT REGISTER SPICLK SPI CLOCK GENERATOR port SPICLK SS Slave MISO MOSI 8-BIT SHIFT REGISTER SPICLK port SS 002aaa437 Fig 19. SPI single master multiple slaves configuration. Master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI Slave 8-BIT SHIFT REGISTER SPICLK SPI CLOCK GENERATOR SS SPICLK SS SPI CLOCK GENERATOR 002aaa499 Fig 20. SPI dual device configuration, where either can be a master or a slave. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 42 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.19 Analog comparators Two analog comparators are provided on the P89LPC912/913/914. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical `1' when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 21. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. Comparator 1 (P0.4) CIN1A CO1 (P0.5) CMPREF VREF CN1 OE1 CMP1 (P0.6) Change Detect CMF1 Interrupt Change Detect Comparator 2 (P0.2) CIN2A CMF2 EC 002aaa496 CN2 Fig 21. Comparator input and output connections. 9.20 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as VREF, is 1.23 V 10 %. 9.21 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt. Possible comparator configurations are shown in Figure 22. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 43 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core CIN1A CMPREF 002aaa490 CIN1A CO1 CMPREF CO1 002aaa491 CMP1 a. CN1, OE1 = 0 0 CIN1A VREF (1.23 V) 002aaa492 b. CN1, OE1 = 0 1 CIN1A CO1 002aaa493 CO1 VREF (1.23 V) CMP1 c. CN1, OE1 = 1 0 CIN2A CMPREF 002aaa494 d. CN1, OE1 = 1 1 CIN2A CO2 VREF (1.23 V) 002aaa495 CO2 e. CN2 = 0 f. CN2 = 1 Fig 22. Comparator configurations. 9.22 Comparator and power reduction modes Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. 9.23 Keypad interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 44 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs. 9.24 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 23 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC912/913/914 User's Manual for more details. WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog oscillator PCLK /32 PRESCALER 8-BIT DOWN COUNTER RESET see note (1) CONTROL REGISTER SHADOW REGISTER FOR WDCON WDCON (A7H) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK 002aaa423 (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 23. Watchdog timer in Watchdog mode (WDTE = `1'). 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 45 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.25 Additional features 9.25.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 9.25.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic `0' so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. 9.26 Flash program memory 9.26.1 General description The P89LPC912/913/914 Flash memory provides in-circuit electrical erasure and programming. The Flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. In-Circuit Programming using standard commercial programmers is available. In addition, In-Application Programming (IAP) and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC912/913/914 Flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC912/913/914 uses VDD as the supply voltage to perform the Program/Erase algorithms. 9.26.2 Features * * * * * * * * 9.26.3 Programming and erase over the full operating voltage range. Byte-erase allowing code memory to be used for data storage. Read/Programming/Erase using ICP. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the Flash for each sector. More than 100,000 minimum erase/program cycles for each byte. 10-year minimum data retention. Flash organization The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 46 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 9.26.4 Flash programming and erasing Different methods of erasing or programming of the Flash are available. The Flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application's firmware. Another option is to use the In-Circuit Programming (ICP) mechanism. This ICP system provides for programming through a serial clock- serial data interface using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 1 kB of user code space. 9.26.5 In-circuit programming (ICP) In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC912/913/914 through a two-wire serial interface. The Philips In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector (with VDD, VSS, RST, clock, and data signals) needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC912/913/914 User's Manual. 9.26.6 In-application programming (IAP-Lite) In-Application Programming is performed in the application under the control of the microcontroller's firmware. The IAP-Lite facility consists of internal hardware resources to facilitate programming and erasing. The Philips In-Application Programming Lite has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC912/913/914 User's Manual. 9.26.7 Using flash as data storage The Flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage. 9.26.8 User configuration bytes Some user-configurable features of the P89LPC912/913/914 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the Flash byte UCFG1. Please see the P89LPC912/913/914 User's Manual for additional details. 9.26.9 User sector security bytes There are four User Sector Security Bytes, each corresponding to one sector. Please see the P89LPC912/913/914 User's Manual for additional details. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 47 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 10. Limiting values Table 12: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg Vxtal Vn IOH(I/O) IOL(I/O) II/O(tot)(max) Ptot(pack) Parameter operating bias ambient temperature storage temperature range voltage on XTAL1, XTAL2 pin to VSS, as applicable voltage on any other pin (except XTAL1, XTAL2) to VSS HIGH-level output current per I/O pin LOW-level output current per I/O pin maximum total I/O current total power dissipation per package based on package heat transfer, not device power consumption Conditions Min -55 -65 -0.5 Max +125 +150 VDD + 0.5 +5.5 8 20 120 1.5 Unit C C V V mA mA mA W [1] The following applies to Limiting values: a) Stresses above those listed under Table 12 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Table 13 "DC electrical characteristics", Table 14 "AC characteristics"and Table 15 "AC characteristics (P89LPC912, P89LPC913)" of this specification are not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 48 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 11. Static characteristics Table 13: DC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol IDD(oper) Parameter power supply current, operating (P89LPC912, P89LPC913) power supply current, Idle mode (P89LPC912, P89LPC913) power supply current, operating (P89LPC914) power supply current, Idle mode (P89LPC914) Power supply current, Power-down mode, voltage comparators powered-down Power supply current, Total Power-down mode VDD fall rate RAM keep-alive voltage negative-going threshold voltage (Schmitt input) positive-going threshold voltage (Schmitt input) hysteresis voltage LOW-level output voltage, all ports IOL = 20 mA IOL = 10 mA IOL = 3.2 mA VOH HIGH-level output voltage, all ports IOH = -8 mA; push-pull mode IOH = -3.2 mA; push-pull mode IOH = -20 A; quasi-bidirectional mode Cig IIL ILI ITL RRST input/output pin capacitance logical 0 input current, all ports logical 1-to-0 transition current, all ports internal reset pull-up resistor VIN = 0.4 V [4] [5] Conditions 3.6 V; 12 MHz 3.6 V; 18 MHz 3.6 V; 12 MHz 3.6 V; 18 MHz 3.6 V; 7.373 MHz 3.6 V; 7.373 MHz 3.6 V [2] [2] [2] [2] [3] Min - Typ[1] 7 11 1.5 4 4 1 - Max 13 16 5.6 6 8 3 70 Unit mA mA mA mA mA mA A IDD(idle) IDD(oper) IDD(idle) IDD(PD) [3] [2][3] IDD(TPD) 3.6 V [2][3] 1.5 0.22VDD VDD - 1.0 VDD - 0.7 VDD - 0.3 -30 10 1 0.4VDD 0.6VDD 0.2VDD 0.6 0.3 0.2 VDD - 0.4 VDD - 0.2 - 5 2 50 0.7VDD 1.0 0.5 0.3 15 -80 10 -450 30 A mV/s mV/s V V V V V V V V V V pF A A A k (dVDD/dt)r VDD rise rate (dVDD/dt)f VRAM Vth(HL) Vth(LH) Vhys VOL input leakage current, all ports VIN = VIL or VIH VIN = 2.0 V at VDD = 3.6 V [6] [7][8] 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 49 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 13: DC electrical characteristics...continued VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol VBO VREF TC(VREF) Parameter brownout trip voltage with BOV = `1', BOPD = `0' bandgap reference voltage bandgap temperature coefficient Conditions 2.4 V < VDD < 3.6 V Min 2.40 1.11 Typ[1] 1.23 10 Max 2.70 1.34 20 Unit V V ppm/ C [1] [2] [3] [4] [5] [6] [7] [8] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper), IDD(PD) specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC912, P89LPC913). The IDD(oper), IDD(PD) specifications are measured with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC914). Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) Port pins source a transition current when used in quasi-bidirectional mode and externally driven from `1' to `0'. This current is highest when VIN is approximately 2 V. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 50 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 12. Dynamic characteristics Table 14: AC characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol fRCOSC Parameter internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to 1 % at Tamb = 25 C internal Watchdog oscillator frequency (nominal f = 400 kHz) oscillator frequency clock cycle CLKLP active frequency glitch rejection, P1.5/RST pin signal acceptance, P1.5/RST pin glitch rejection, any pin except P1.5/RST signal acceptance, any pin except P1.5/RST External clock (P89LPC912, P89LPC913) tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tDVXH HIGH time LOW time rise time fall time serial port clock cycle time output data set-up to clock rising edge output data hold after clock rising edge input data hold after clock rising edge see Figure 29 see Figure 29 see Figure 29 see Figure 29 see Figure 28 see Figure 28 see Figure 28 see Figure 28 33 33 16 tCLCL 13 tCLCL 150 tCLCL - tCLCX tCLCL - tCHCX 8 8 tCLCL + 20 0 33 33 1333 1083 150 8 8 103 0 ns ns ns ns ns ns ns ns ns see Figure 29 Conditions Variable clock Min 7.189 Max 7.557 fosc = 12 MHz Min 7.189 Max 7.557 MHz Unit fWDOSC 320 520 320 520 kHz Crystal oscillator (P89LPC912, P89LPC913) fosc tCLCL fCLKP Glitch filter 125 50 50 15 125 50 50 15 ns ns ns ns 0 83 0 12 8 MHz ns MHz Shift register (UART mode 0 - P89LPC913, P89LPC914) input data valid to clock rising edge see Figure 28 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 51 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 14: AC characteristics...continued VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock Min SPI interface fSPI Operating frequency 2.0 MHz (Slave) 3.0 MHz (Master) tSPICYC Cycle time 2.0 MHz (Slave) 3.0 MHz (Master) tSPILEAD Enable lead time (Slave) 2.0 MHz tSPILAG Enable lag time (Slave) 2.0 MHz tSPICLKH SPICLK high time Master Slave tSPICLKL SPICLK low time Master Slave tSPIDSU tSPIDH tSPIA tSPIDIS Data set-up time (Master or Slave) see Figure 24, 25, 26, 27 Data hold time (Master or Slave) Access time (Slave) Disable time (Slave) 2.0 MHz tSPIDV Enable to output data valid 2.0 MHz 3.0 MHz tSPIOH Output data hold time see Figure 24, 25, 26, 27 see Figure 24, 25, 26, 27 0 0 0 240 167 0 240 167 ns ns ns see Figure 24, 25, 26, 27 see Figure 26, 27 see Figure 26, 27 0 240 240 ns see Figure 24, 25, 26, 27 2 3 CCLK CCLK fosc = 12 MHz Min Max Unit Max 0 see Figure 24, 25, 26, 27 6 4 CCLK CCLK CCLK 6 CCLK 4 0 - 2.0 - MHz MHz - 500 - - ns ns see Figure 26, 27 250 see Figure 26, 27 250 see Figure 24, 25, 26, 27 2 3 CCLK CCLK - 250 - ns - 250 - ns - 340 190 - ns ns 120 340 190 100 100 0 120 ns ns ns ns ns 100 100 0 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 52 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 14: AC characteristics...continued VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol tSPIR Parameter Rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF Fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) [1] Conditions see Figure 24, 25, 26, 27 Variable clock Min Max fosc = 12 MHz Min Max Unit see Figure 24, 25, 26, 27 - 100 2000 - 100 2000 ns ns 100 2000 - 100 2000 ns ns Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 53 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 15: AC characteristics (P89LPC912, P89LPC913) VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol fRCOSC Parameter internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to 1 % at Tamb = 25 C internal Watchdog oscillator frequency (nominal f = 400 kHz) oscillator frequency clock cycle CLKLP active frequency glitch rejection, P1.5/RST pin signal acceptance, P1.5/RST pin glitch rejection, any pin except P1.5/RST signal acceptance, any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL fSPI HIGH time LOW time rise time fall time Operating frequency 3.0 MHz (Slave) 4.5 MHz (Master) tSPICYC Cycle time 3.0 MHz (Slave) 4.5 MHz (Master) see Figure 24, 25, 26, 27 6 4 CCLK CCLK [2] Conditions Variable clock Min 7.189 Max 7.557 fosc = 18 MHz Min 7.189 Max 7.557 Unit MHz fWDOSC 320 520 320 520 kHz Crystal oscillator fosc tCLCL fCLKP Glitch filter 125 50 50 15 125 50 50 15 ns ns ns ns 0 55 0 18 8 MHz ns MHz see Figure 29 see Figure 29 see Figure 29 see Figure 29 see Figure 29 22 22 - tCLCL - tCLCX tCLCL - tCHCX 5 5 22 22 - 5 5 ns ns ns ns SPI interface 0 CCLK 6 CCLK 4 0 - 3 4.5 MHz MHz - 333 222 - ns ns 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 54 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 15: AC characteristics (P89LPC912, P89LPC913)...continued VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol tSPILEAD Parameter Enable lead time (Slave) 3.0 MHz tSPILAG Enable lag time (Slave) 3.0 MHz tSPICLKH SPICLK high time Master Slave tSPICLKL SPICLK low time Master Slave tSPIDSU tSPIDH tSPIA tSPIDIS Data set-up time (Master or Slave) see Figure 24, 25, 26, 27 Data hold time (Master or Slave) Access time (Slave) Disable time (Slave) 3.0 MHz tSPIDV Enable to output data valid 3.0 MHz 4.5 MHz tSPIOH tSPIR Output data hold time Rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) see Figure 24, 25, 26, 27 see Figure 24, 25, 26, 27 100 2000 100 2000 ns ns see Figure 24, 25, 26, 27 0 0 0 160 111 0 160 111 ns ns ns see Figure 24, 25, 26, 27 see Figure 26, 27 see Figure 26, 27 0 160 160 ns see Figure 24, 25, 26, 27 2 3 CCLK CCLK Conditions see Figure 26, 27 Variable clock Min Max fosc = 18 MHz Min Max Unit 250 see Figure 26, 27 250 see Figure 24, 25, 26, 27 2 3 CCLK CCLK - 250 - ns - 250 - ns - 111 167 - ns ns 80 111 167 100 100 0 80 ns ns ns ns ns 100 100 0 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 55 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Table 15: AC characteristics (P89LPC912, P89LPC913)...continued VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol tSPIF Parameter Fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) [1] [2] Conditions see Figure 24, 25, 26, 27 Variable clock Min Max fosc = 18 MHz Min Max Unit - 100 2000 - 100 2000 ns ns Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. SS tCLCL tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPICLKL tSPIR tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR MSB/LSB in tSPIDV MOSI (output) tSPIF Master MSB/LSB out Master LSB/MSB out 002aaa156 Fig 24. SPI master timing (CPHA = 0). 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 56 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core SS tCLCL tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKH tSPICLKL tSPIR SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIDV tSPIR Master MSB/LSB out Master LSB/MSB out MSB/LSB in tSPIDV MOSI (output) tSPIF 002aaa157 Fig 25. SPI master timing (CPHA = 1). SS tSPIR tSPIR tSPILAG tSPIR tSPILEAD tSPIF tCLCL tSPICLKH tSPICLKL SPICLK (CPOL = 0) (input) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (input) tSPIA MISO (output) tSPIOH tSPIDV Slave MSB/LSB out tSPIOH tSPIDV tSPIOH tSPIDIS Slave LSB/MSB out Not defined tSPIDSU MOSI (input) tSPIDH tSPIDSU tSPIDSU tSPIDH MSB/LSB in LSB/MSB in 002aaa158 Fig 26. SPI slave timing (CPHA = 0). 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 57 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core SS tSPIR tSPIR tSPILAG tSPIR tSPILEAD tSPIF tCLCL tSPICLKH tSPICLKL SPICLK (CPOL = 0) (input) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) Not defined Slave MSB/LSB out Slave LSB/MSB out tSPIOH tSPIDV tSPIOH tSPIDV tSPIDIS tSPIDSU MOSI (input) tSPIDH tSPIDSU tSPIDSU tSPIDH MSB/LSB in LSB/MSB in 002aaa159 Fig 27. SPI slave timing (CPHA = 1). tXLXL Clock tQVXH Output Data 0 Write to SBUF Input Data Clear RI Set RI 002aaa425 tXHQX 1 tXHDX Set TI Valid Valid Valid Valid Valid Valid Valid Valid 2 3 4 5 6 7 tXHDV Fig 28. Shift register mode timing. VDD - 0.5 V 0.45 V 0.2 VDD + 0.9 0.2 VDD - 0.1 V tCHCX tCHCL tCLCX tC tCLCH 002aaa416 Fig 29. External clock timing. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 58 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 13. Comparator electrical characteristics Table 16: Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol VIO VCR CMRR Parameter offset voltage comparator inputs common mode range comparator inputs common mode rejection ratio response time comparator enable to output valid IIL [1] [1] Conditions Min 0 - Typ 250 - Max 20 VDD - 0.3 -50 500 10 10 Unit mV V dB ns s A input leakage current, comparator 0 < VIN < VDD - This parameter is characterized, but not tested in production. 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 59 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 14. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 30. TSSOP14 package outline (SOT402-1). 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 60 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 15. Revision history Table 17: Rev Date 03 20041217 Revision history CPCN Description Product data (9397 750 14468) Modification: * 02 01 20031212 20030711 - Added 18 MHz information. Product data (9397 750 12286); ECN 01-A14930 dated 10 December 2003. Objective data (9397 750 11537) 9397 750 14468 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 61 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 16. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 14468 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 17 December 2004 62 of 63 Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.10.1 9.11 9.11.1 9.11.2 9.11.3 9.11.4 9.11.5 9.11.6 9.11.7 9.12 9.12.1 9.12.2 9.13 9.13.1 9.13.2 9.13.3 9.14 9.15 9.15.1 9.15.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Product comparison . . . . . . . . . . . . . . . . . . . . . . . . . 15 Special function registers. . . . . . . . . . . . . . . . . . . . . 15 Functional description . . . . . . . . . . . . . . . . . . . . . . . 26 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 26 Low speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Medium speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . 26 High speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock output (P89LPC912, P89LPC913) . . . . . . . . . 27 On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 27 Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 27 External clock input option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 29 CPU Clock (CCLK) modification: DIVM register . . . 29 Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 30 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Quasi-bidirectional output configuration. . . . . . . . . . 32 Open-drain output configuration. . . . . . . . . . . . . . . . 33 Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 33 Push-pull output configuration . . . . . . . . . . . . . . . . . 33 Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 33 Additional port features . . . . . . . . . . . . . . . . . . . . . . 34 Power monitoring functions . . . . . . . . . . . . . . . . . . . 34 Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 34 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 35 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 36 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Mode 6 (P89LPC912, P89LPC914) . . . . . . . . . . . . . 37 Timer overflow toggle output (P89LPC912, P89LPC914) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.16 Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 37 9.17 UART (P89LPC913, P89LPC914) . . . . . . . . . . . . . . 37 9.17.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.17.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.17.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.17.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.17.5 Baud rate generator and selection . . . . . . . . . . . . . . 38 9.17.6 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.17.7 Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.17.8 Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 39 9.17.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.18 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . 39 9.18.1 Typical SPI configurations. . . . . . . . . . . . . . . . . . . . . 41 9.19 Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.20 Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 43 9.21 Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 43 9.22 Comparator and power reduction modes . . . . . . . . . 44 9.23 Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 44 9.24 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.25 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.25.1 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.25.2 Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.26 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 46 9.26.1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.26.3 Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.26.4 Flash programming and erasing . . . . . . . . . . . . . . . . 47 9.26.5 In-circuit programming (ICP). . . . . . . . . . . . . . . . . . . 47 9.26.6 In-application programming (IAP-Lite) . . . . . . . . . . . 47 9.26.7 Using flash as data storage . . . . . . . . . . . . . . . . . . . 47 9.26.8 User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 47 9.26.9 User sector security bytes . . . . . . . . . . . . . . . . . . . . 47 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 51 13 Comparator electrical characteristics . . . . . . . . . . . 59 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.15.3 9.15.4 9.15.5 9.15.6 (c) Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 17 December 2004 Document order number: 9397 750 14468 |
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